Architectural Optimizations in Multi-Core Processors

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Price: ₹5,717.00
(as of Oct 23, 2025 12:54:11 UTC – Details)


The quest for greater computational power is never-ending. Recently, the architectural trend has shifted from improving single-threaded application performance to improving multi-threaded application per-formance. Thus, multi-core processors have been increasingly popular. To achieve concurrent execution of threads on multi-core processors, applications must be explicitly restructured to exploit parallelism, either by programmers or compilers. However, conventional parallel pro-gramming models may introduce overhead due to synchronization and communications among threads in multi-threaded applications. This book presents three architectural optimizations to improve thread-based synchronization and communications support in multi-core processors. Register-Based Synchronization (RBS) uses hardware registers efficiently to provide synchronization support in multi-core processors. Prepushing is a software controlled data forwarding technique to provide communications support in multi-core processors. Software Controlled Eviction (SCE) improves shared cache communications by placing shared data in shared caches.
Publisher ‏ : ‎ VDM Verlag (18 November 2008)
Language ‏ : ‎ English
Paperback ‏ : ‎ 144 pages
ISBN-10 ‏ : ‎ 363910157X
ISBN-13 ‏ : ‎ 978-3639101577
Item Weight ‏ : ‎ 204 g
Dimensions ‏ : ‎ 15.01 x 0.84 x 22 cm
Country of Origin ‏ : ‎ India

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